1. Field
Example embodiments relate to a semiconductor device, and more particularly, to a non-volatile memory device including a storage node layer for storing charges and a method of fabricating the same.
2. Description of the Related Art
FIG. 1 is a plan view of a conventional non-volatile memory device. Referring to FIG. 1, the non-volatile memory device includes buried bit line regions 55 and control gate electrodes 70 which extend across the buried bit line regions 55. Dopant may be doped in a semiconductor substrate 50 to define the buried bit line regions 55. Since an isolation layer in a cell region is not required in a non-volatile memory device as shown in FIG. 1, the non-volatile memory device may have a relatively small size.
However, the buried bit line regions 55 in conventional non-volatile memory devices generally have higher resistances than metal lines. Thus, the resistances of the buried bit line regions 55 are relatively high in an array structure in which the buried bit line regions 55 have long lengths. Therefore, the buried bit line regions 55 arranged beside the control gate electrodes 70 are connected to metal lines through contact structures 60. However, the contact structures 60 increase the size of the non-volatile memory device and thus, reduce the integration of the conventional non-volatile memory device as shown in FIG. 1.
Further, if distances between the buried bit line regions 55 are shortened, the integration of the non-volatile memory device may be increased. However, in this case, the reliability of the conventional non-volatile memory device is significantly decreased due to a short channel effect.